Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) cell comprises a plurality of memory cells which are used to store large quantities of information. Each memory cell typically includes a capacitor for storing electric charge and a field effect transistor (FET) for opening and closing charge and discharge passages of the capacitor. The number of cells (and corresponding bits of memory capacity) of DRAM integrated circuit chips has been increasing by approximately 4.times. every three years; this has been achieved by reducing memory cell size. Unfortunately, the smaller memory cell size also results in less area to fabricate the capacitor.
Moreover, as DRAM cell dimensions are scaled down with each successive generation, the cross-sectional area of the deep trench storage capacitor diminishes inversely with the square of the ground rule, while the trench depth has remained approximately constant. This change in trench geometry results in a large increase in the series resistance contributed by the polysilicon electrode contained within the deep trench. The increased series resistance, in turn, may adversely limit the speed at which the corresponding memory cell can be accessed.
One approach known in the prior art to decrease the series resistance of DRAM trench capacitors is to increase the doping concentration of the deep trench polysilicon. This approach however only provides a marginal reduction in series resistance and thus has limited applicability in fabricating DRAM cells of decreased dimension.
In view of the state of the prior art, there is a continued need for new manufacturing processes and/or designs which more effectively address the problem of series resistance in the context of trench capacitors and devices incorporating such capacitors, e.g. DRAM chips.